Generally, a reduced swing differential signaling (RSDS) system or a mini low voltage differential signaling (mini-LVDS) system is used for an interface between a timing controller and a source driver. However, such a system has a drawback in that it is necessary to use a large number of signal lines and it is difficult to achieve high-frequency operation. An advanced intra Panel interface (AIPI) has been proposed for a transmission system capable of reducing the number of signal lines while achieving high-frequency operation.
FIG. 1 is a waveform diagram illustrating a signal transmission type of an AIPI. FIG. 2 is a circuit diagram illustrating a receiver stage of the AIPI; however, this system has a number of drawbacks. In accordance with the concept of generating a clock signal in this system, a pair of input signals IN and INB are compared with a pair of reference signals REFH and REFL, respectively, in order to detect a state in which the paired input signals IN and INB have levels beyond the levels of the paired reference signals REFH and REFL in a clock period, respectively. However, when the reference signals REFH and REFL are severely varied due to variations in process, supply voltage, temperature, etc. and in particular, when the signal levels of the paired input signals IN and INB are severely varied, it is difficult to discriminate a clock level and a data level. In this case, a clock clk may not be generated in the clock period. Erroneously, a clock clk may be generated in a data period. No clock may be generated in any period. Also, a transition time difference may occur due to a level difference between clock and data signals, so that the clock and data reconstituted in the receiver may be desynchronized, and the timing margin of the data latching operation may be limited.